Silicon Reliability Engineer

Company: Google
Location: Mountain View
Posted on: April 2, 2026

Job Description:

Minimum qualifications: Bachelor's degree in Electrical Engineering, Material Science, Mechanical Engineering, Physics, or a related technical field, or equivalent practical experience. 6 years of experience in logic Application-Specific Integrated Circuit (ASIC) device and package reliability Joint Electron Device Engineering Council (JEDEC) qualification, including High Temperature Operating Life (HTOL), Electrostatic Discharge (ESD), Latch-Up (LU), Temperature Cycling (TC), and Highly Accelerated Stress Test (HAST). Experience in semiconductor device physics, transistor reliability, CMOS technology and manufacturing. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Material Science, Mechanical Engineering, Physics, or a related technical field. 10 years of experience in reliability testing and qualification of ICs to JEDEC standards. Experience in semiconductor failure analysis tools SEM, TEM, FIB, CSAM, Nanoprobe, and X-Ray. Experience in product engineering, including DFT, HTOL test coverage, and HTOL test hardware design. Experience in semiconductor device physics, transistor reliability (e.g., HCI, BTI, TDDB, EM), advanced CMOS logic technology and manufacturing (5nm-2nm nodes). Experience in statistical analysis (e.g., Design Expert, JMP, Weibull), lifetime, FIT, and failure rate projection of semiconductor components and ICs. About the job As a Reliability Engineer, you will play a key role in creating new consumer electronic products that meet a high bar for reliability and performance. You will work closely with the product management and design engineering teams to define standards, specify tests, and then supervise test execution and failure analysis. A broad engineering background and command of statistical methods will help to inform design of new products. Your strong interpersonal and communication skills will be key to ensuring adoption of your technical recommendations. In this role, you will lead the Integrated Circuit (IC) product reliability qualification of Pixel Systems-on-Chips (SOCs) and their Power Integrated Management Integrated Circuits (PIMICs), designed and developed by the Silicon Team, to Joint Electron Device Engineering Council (JEDEC) standards. You will cover the qualification of Systems-on-Chips (SOCs) in Pixel systems to meet Pixel customer usage conditions. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. The US base salary range for this full-time position is $159,000-$231,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Define custom silicon Application-Specific Integrated Circuit (ASIC) reliability specifications based on Joint Electron Device Engineering Council (JEDEC) standards and Google product field usage conditions. Execute Application-Specific Integrated Circuit (ASIC) product reliability qualification tests, including High Temperature Operating Life (HTOL), Electrostatic Discharge (ESD), Latch-Up (LU), Early Life Failure Rate (ELFR), Temperature Cycling (TC), and Biased Highly Accelerated Stress Test (BHAST) testing. Utilize statistical methods and failure analysis to estimate System-on-Chip (SOC) life times and evaluate Complementary Metal-Oxide-Semiconductor (CMOS) technology reliability. Collaborate with cross-functional internal and external teams, such as Complementary Metal-Oxide-Semiconductor (CMOS) foundries, Outsourced Semiconductor Assembly and Tests (OSATs), and third-party qualification facilities.

Keywords: Google, Walnut Creek , Silicon Reliability Engineer, Engineering , Mountain View, California